read_file -f verilog counter.v
# Comandos alternativos:
# analyze -library WORK -format verilog counter.v
# elaborate counter -architecture verilog -library WORK
#
#
current_design counter
link

##
set_dont_use c35_CORELIB.db:c35_CORELIB/OAI212
set CLOCK clk

# definir as condicoes de operacao:
set_operating_conditions -library c35_CORELIB WORST

# definir o perÃ­odo do sinal de relogio:
create_clock -period 100 $CLOCK
set_clock_uncertainty 0.2 $CLOCK

# fixe os tempos de hold dos flip-flops:
set_fix_hold $CLOCK

set_fix_multiple_port_nets -all

set OUTPUT_LOAD [ load_of "c35_IOLIB_4M/BU12P/A"  ]
set_load $OUTPUT_LOAD [all_outputs]

set_driving_cell -lib_cell ICP -library c35_IOLIB_4M [all_inputs]
set_driving_cell -lib_cell ICCK16P -library c35_IOLIB_4M  "clk rst"

# Optimizar
compile

# Escrever os resultados
change_names -rules verilog -hierarchy
write -hierarchy -format ddc  -output counter_final.ddc
write -hierarchy -format verilog -output counter_final.v

# Registar informacao sobre os resultados
report_area                  > counter.rtl.reports
report_timing               >> counter.rtl.reports
report_reference            >> counter.rtl.reports
check_design                >> counter.rtl.reports
report_constraints -verbose >> counter.rtl.reports
report_hierarchy            >> counter.rtl.reports
report_port                 >> counter.rtl.reports
report_power                 >> counter.rtl.reports
exit
